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Feb 27, 2012 - Mar 1, 2012
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Mar 29, 2012 - Mar 29, 2012
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The PC202 brings the massively parallel signal processing capabilities of the picoArray to cost-constrained high volume applications. Capable of implementing a complete software-defined WCDMA modem in a single device, the PC202 is available in two versions.
The standard device integrates a 248-element picoArray and 280MHz ARM926EJ-S processor with application accelerators for forward error correction, FFT/IFT, security and encryption. An enhanced (-10) version with a larger, 273-element picoArray provides extra processing headroom, allowing designers to implement value-added features and differentiate their end products.
Both variants include a complete DDR-II DRAM controller and a flexible interface for the radio and RF sections.
The performance of a single PC202 device at 160MHz is summarized below:
| Operation | Peak / sec. / device (PC202 @ 160MHz) | ||
| . | PC202 | PC202-10 | Units |
| MIPS | 230 | 262 | GIPS |
| MACs | 31 | 35 | GMAC/s |
| 16-bit MPYs | 8 | 9 | GMUL/s |
| FFT (aggregate) | 80 | 80 | MS/s |
| Crypto Engine | 12 | 12 | Mbits/s |
| Turbo Code (8 iterations) | 8 | 8 | Mbits/s |
| Viterbi | 8 | 8 | Mbits/s |
| Reed-Solomon | 8 | 8 | Mbits/s |
| Correlator | 40 | 40 | Mbits/s |
| ADI | 1x160 | 1x160 | MS/s |
| ARM | 280 | 280 | MHz |
The devices’ integrated ARM9 subsystem provides a high performance processor core allowing implementation of control code such as that required for MAC functions for access points and mesh network nodes. The ARM9 subsystem includes large on-chip memory, cache, and high performance interfaces to the picoArray and external bus interfaces.
The PC202 is the heart of the PC7202 femtocell/access point development platform and the target processor for the Picochip PC8208 and PC8209 WCDMA/HSDPA/HSUPA femtocell base station reference designs. In addition it is an ideal vehicle for other applications in advanced wireless, test and measurement and medical imaging.